Split gate non-volatile memory (NVM) circuits have achieved widespread adoptions for code and data storage applications. An important aspect of split gate NVM circuits is their performance, which includes endurance (number of programming or write/erase cycles) and data retention after write/erase cycling. Memory operations, such as programming and erasing, may involve, for example, charging or discharging electrons from a floating gate of the split gate NVM cell. The charging and discharging of electrons may be achieved by Hot Carrier Injection (HCI) or Fowler-Nordheim (FN) tunneling.
Current split-gate NVM cell suffers several limitations, such as scalability issues or program disturbance due to poor punch through immunity. As such, it is desirable to provide a split-gate NVM cell with improved scalability, increased program/erase speed, minimized program disturbance and with improved endurance.